アカリクキャリア

JOB ID：118322

非公開求人

給与	400万円〜 900万円
業種	メーカー
勤務地	海外
業務内容	【Essential Responsibilities 】 Design and PDK department, known as the Enablement team, is a crucial pillar in Rapidus to deliver process design kit (PDK) to external customers to enable their turn-key product design to the market. In the Enablement team, the PDK group will directly enable circuit design on Rapidus’s innovative technologies. As a member of the Enablement team, you will be at the forefront of co-optimizing Rapidus's industry leading edge process technology which allows customers with diverse design needs to enable products for artificial intelligence (AI) applications. The PDK group is responsible for the development, maintenance, delivery and support of PDKs used by external customers and internal designers. This position involves developing and maintaining software for various PDK components such as DRC, LVS and RC Extraction using industry standard EDA tools. 【Other Responsibilities】・ Develop, maintain and improve Rapidus PDK and PDK-QA flows. ・ Create PDK related documentation. ・ Support for external and internal customer’s PDK related questions. ・ Work with EDA/IP vendors and Rapidus technology development team for continuous PDK improvement. The candidate should also exhibit the following behavioral traits and/or skills: ・ Analytical problem solving and troubleshooting skills. ・ Written and oral communication skills ・ Teamwork and collaboration skills ・ Self-motivated and driven achievement both on-site and off-site work.
応募資格	必須スキル・経験 Required Qualifications ? Master’s degree with 10+ years of experience in Electrical Engineering or a related STEM field ? Deep understanding of the design to tape-out workflow (Schematic, Simulation, Layout, Physical Verification, RC Extraction, MASK). ? 7+ years of experience in one or more of the following: -Development of DRC runsets for Siemens Calibre, Cadence Pegasus and Synopsys ICV -Development of LVS runsets for Siemens Calibre, Cadence Pegasus and Synopsys ICV -Development of PEX(Parasitic Extraction) runsets for Synopsys StarRC, Cadence Quantus and Siemens xACT 歓迎スキル・経験 Preferred Qualifications ? Hands-on experience in one or more of the following: Python, TCL, SKILL, shell scripting, Perl ? Basic understanding of device physics and foundry process technology ? Basic understanding of Analog and Mixed-Signal circuit design ? Familiarity with version control tools and bug tracking systems ? Experience with customer support
福利厚生 / 待遇	・通勤手当・残業手当・健康保険・厚生年金・雇用保険・労災保険
勤務時間	フレックスタイム制（フルフレックス）標準労働時間帯 9:00～17:30（休憩60分） 1日の標準労働時間 7時間30分
休日休暇	完全週休2日制（土日、祝）【年間休日】 120日【休暇制度】年末年始休暇創立記念日（8月10日）年次有給休暇（初年度6日-10日、勤続年数に応じて最大20日）