JOB ID:118315
| 給与 | 400万円 〜 900万円 |
|---|---|
| 業種 | メーカー |
| 勤務地 | 北海道,東京都,海外 |
| 業務内容 | Rapidus is a leading innovator in cutting-edge digital chip design. We are looking for a talented and experienced Digital Chip Design Engineer to join our team, focusing on Standard Cell Development and Design Technology Co-Optimization (DTCO). In this role, you will be instrumental in enabling high-performance and low-power digital chips for our next-generation products, by driving the convergence of library design and process technology. You will have the opportunity to work with state-of-the-art technology in a global environment, actively contributing to our advanced product development. Key Responsibilities: - Design, evaluate, and optimize standard cell libraries for advanced technology nodes. - Plan and execute DTCO (Design Technology Co-Optimization) activities, strengthening the collaboration between circuit design and process technology to achieve optimal PPA (Power, Performance, Area) targets. - Develop and improve custom layout, characterization, and verification flows. - Design with a keen understanding of design rules, process variations, and reliability requirements. - Collaborate closely with design teams, process and device development teams, and EDA teams. - Evaluate and introduce new design methodologies and tools to meet PPA goals. - Engage in technical discussions and collaborations with IP vendors and EDA venders. - Document and maintain design data. |
| 応募資格 | 必須スキル・経験 Required Skills & Experience - Bachelor's degree or higher in Electrical Engineering, Electronics Engineering, Physics, or a related field. - 5+ years of hands-on experience in digital IC design, specifically in custom cell, standard cell, or memory design. - Proven design experience with advanced CMOS technology nodes (e.g., 7nm, 5nm, 3nm). - In-depth knowledge and experience in standard cell library characterization and verification. - Strong understanding of PDK (Process Design Kit) and design rules. - Proficiency with EDA tools such as Cadence Virtuoso, Synopsys Custom Compiler, HSPICE, Spectre, PrimeTime, and Liberate - Understanding of DTCO concepts and a strong willingness to contribute to related activities. - Experience with scripting languages for automation (e.g., Python, Perl, Tcl). - Excellent analytical and problem-solving skills. - Business-level English proficiency, capable of technical discussions with international engineers. - English communication skills. 歓迎スキル・経験 Preferred Skills & Experience - Practical experience or significant contributions to DTCO activities. - Design experience with FinFET or GAAFET technologies. - Knowledge of physical design (floor planning, place & route). - Understanding of reliability issues (IR drop, EM, ESD, etc.). - Experience applying machine learning or AI to design optimization. - Team management or project leadership experience. 求める人物像 Desired Personality Traits - Highly motivated to continuously learn new technologies and trends. - Ability to approach and solve complex technical challenges logically. - Strong team player who can collaborate effectively with team members from diverse backgrounds to achieve common goals. - Detail-oriented with a commitment to delivering high-quality results. - Highly responsible and able to drive tasks autonomously. |
| 福利厚生 / 待遇 | ・通勤手当 ・残業手当 ・健康保険 ・厚生年金 ・雇用保険 ・労災保険 |
| 勤務時間 | フレックスタイム制(フルフレックス) 標準労働時間帯 9:00~17:30(休憩60分) 1日の標準労働時間 7時間30分 |
| 休日休暇 | 完全週休2日制(土日、祝) 【年間休日】 120日 【休暇制度】 年末年始休暇 創立記念日(8月10日) 年次有給休暇(初年度6日-10日、勤続年数に応じて最大20日) |