アカリクキャリア

JOB ID：118314

非公開求人

給与	400万円〜 900万円
業種	メーカー
勤務地	北海道,東京都,海外
業務内容	apidus is a leading foundry at the forefront of semiconductor innovation, enabling the next generation of integrated circuits. We are seeking a highly skilled and experienced Test Chip Design Engineer to join our team. In this role, you will be responsible for the physical design and PPA (Power, Performance, Area) analysis of cutting-edge test chips, critical for validating and characterizing our advanced process technologies. You will play a pivotal role in bridging the gap between process development and product design, ensuring our technology offerings meet the demanding requirements of our global customers. This position offers a unique opportunity to work with the latest process nodes and design methodologies, contributing directly to the future of semiconductor manufacturing. Key Responsibilities As a Test Chip Design Engineer, your responsibilities will include: - Test Chip Physical Design and PPA Analysis: - Backend (BE) Implementation and Related Flow Development: Drive the full backend implementation flow, from chip-level planning and PG (Power/Ground) network design to floorplan, place, CTS (Clock Tree Synthesis), route, power analysis (PDNA sign-off), and comprehensive physical verification. - Design Methodology and EDA Tool Utility Development: Develop and enhance design methodologies and associated EDA tool utilities specifically for backend implementation. This includes creating solutions for challenges arising from new process technologies and developing utilities to support our customers effectively. - Technology Benchmark: Conduct detailed technology benchmarking to thoroughly understand and evaluate the PPA characteristics of new process technologies. - Collaborate closely with process development teams, circuit design teams, and EDA vendors to define and implement robust design flows. - Analyze and debug complex physical design issues, including timing, power, and physical verification failures. - Contribute to the continuous improvement of design processes and methodologies. - Document design specifications, methodologies, and results clearly and concisely.
応募資格	必須スキル・経験 Required Skills & Experience : - Bachelor's degree or higher in Electrical Engineering, Electronics Engineering, or a related field. - 5+ years of hands-on experience in digital backend IC design, with a strong focus on physical design and sign-off. - Proven expertise in the full physical design flow: floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and physical verification (DRC/LVS/Antenna). - Solid experience with power analysis (PDNA sign-off) and static timing analysis (STA). - Proficiency with industry-standard EDA tools for physical design (e.g., Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, RedHawk, Calibre). - Experience in scripting languages (e.g., Tcl, Python, Perl) for design automation and flow development. - Strong understanding of advanced CMOS process technologies and their impact on physical design. - Excellent analytical and problem-solving skills, with a keen eye for detail. - Business-level English proficiency, capable of technical discussions with international engineers. - English communication skills. 歓迎スキル・経験 Preferred Skills & Experience - Experience in test chip design or IP development within a foundry environment. - Familiarity with advanced technology nodes (e.g., 7nm, 5nm, 3nm). - Knowledge of FinFET or GAAFET architectures. - Experience with custom layout design or standard cell library development. - Prior experience in developing custom design methodologies or CAD utilities. - Understanding of reliability issues (e.g., EM, IR drop, ESD) from a physical design perspective. - Project leadership or mentoring experience. 求める人物像 Desired Personality Traits - Proactive and self-motivated, with a strong drive to innovate and solve complex technical challenges. - Highly collaborative, able to work effectively with cross-functional teams across different geographies. - Detail-oriented and committed to delivering high-quality, reliable designs. - Continuously eager to learn and adapt to new technologies and methodologies. - Strong communication skills to articulate complex technical concepts clearly.
福利厚生 / 待遇	・通勤手当・残業手当・健康保険・厚生年金・雇用保険・労災保険
勤務時間	フレックスタイム制（フルフレックス）標準労働時間帯 9:00～17:30（休憩60分） 1日の標準労働時間 7時間30分
休日休暇	完全週休2日制（土日、祝）【年間休日】 120日【休暇制度】年末年始休暇創立記念日（8月10日）年次有給休暇（初年度6日-10日、勤続年数に応じて最大20日）