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JOB ID：118311

非公開求人
非公開求人
給与 400万円 〜 900万円
業種 メーカー
勤務地 北海道,東京都,海外
業務内容 Location: Albany, NY; Santa Clara, CA; or Tokyo, Japan
Team: Enablement Team ? Technology Development

Job Description
We are seeking a highly motivated and experienced Senior DFT Engineer to join our Enablement Team supporting the development of advanced semiconductor process technologies at the 2nm node and beyond. You will lead the Design-for-Test (DFT) implementation of large-scale test chips that are critical for enabling and validating our next-generation manufacturing processes.
In this role, you will focus on scan insertion, ATPG, memory BIST, and other DFT methodologies, while also supporting yield analysis and EDA tool collaboration to improve design quality and test efficiency. You will work closely with RTL designers, physical design teams, process integration engineers, and EDA partners to ensure robust DFT infrastructure across our global sites.

Responsibilities
? Define and implement DFT architectures for technology development test chips, focusing on scan, boundary scan, and memory BIST.
? Function and timing verification of implemented DFT circuit, evaluate test coverage with DFT simulation (ATPG, BIST, Fault simuation).
? Propose the best test solution with analysis among test coverage, test cost, test time
? Collaborate with design teams to integrate DFT features from RTL through physical implementation.
?
? Develop and validate ATPG and MBIST patterns; support test bring-up and debug on silicon.
? Analyze test data from silicon to identify systematic issues and improve process yield.
? Engage with EDA vendors to evaluate and improve DFT tools and methodologies for advanced nodes.
? Document best practices and contribute to the enablement of scalable DFT flows across future technology nodes.
? Support cross-functional teams spanning design, process, product engineering, and reliability.
応募資格 必須スキル・経験
Minimum Qualifications
? MS or PhD in Electrical Engineering, Computer Engineering, or a related field.
? 5+ years of experience in DFT development, preferably including advanced node designs or large-scale test chips.
? Strong expertise in scan-based DFT, ATPG, compression, and memory BIST techniques.
? Hands-on experience with commercial DFT tools (e.g., Synopsys TestMax, Siemens Tessent, Cadence Modus).
? Understanding of RTL-to-GDS flows and DFT timing considerations.
? Practical experience in silicon bring-up, failure analysis, and yield improvement.
? Excellent communication skills and the ability to work in a cross-site, cross-functional team.

歓迎スキル・経験
Preferred Qualifications
? Experience with DFT implementation for sub-5nm technologies.
? Experience with DFT implementation for chiplet SOCs.
? Familiarity with data analysis tools and methodologies used in yield learning.
? Strong scripting ability (Python, Tcl, Perl) for automation of DFT and test flows.
? Knowledge of test chip development for process technology enablement.
? Japanese language proficiency is a plus but not required.
福利厚生 / 待遇 ・通勤手当
・残業手当
・健康保険
・厚生年金
・雇用保険
・労災保険
勤務時間 フレックスタイム制（フルフレックス）
標準労働時間帯 9:00～17:30（休憩60分）
1日の標準労働時間 7時間30分
休日休暇 完全週休2日制（土日、祝）

【年間休日】
120日

【休暇制度】
年末年始休暇
創立記念日（8月10日）
年次有給休暇（初年度6日-10日、勤続年数に応じて最大20日）